Extreme Statistics in Nanoscale Memory Design
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Beschreibung
Extreme Statistics in Nanoscale Memory Design brings together some of the world’s leading experts in statistical EDA, memory design, device variability modeling and reliability modeling, to compile theoretical and practical results in one complete reference on statistical techniques for extreme statistics in nanoscale memories.
The work covers a variety of techniques, including statistical, deterministic, model-based and non-parametric methods, along with relevant description of the sources of variations and their impact on devices and memory design. Specifically, the authors cover methods from extreme value theory, Monte Carlo simulation, reliability modeling, direct memory margin computation and hypervolume computation. Ideas are also presented both from the perspective of an EDA practitioner and a memory designer to provide a comprehensive understanding of the state-of -the-art in the area of extreme statistics estimation and statistical memory design.
Extreme Statistics in Nanoscale Memory Design is a useful reference on statistical design of integrated circuits for researchers, engineers and professionals.
Knowledge exists: you only have to ?nd it VLSI design has come to an important in?ection point with the appearance of large manufacturing variations as semiconductor technology has moved to 45 nm feature sizes and below. If we ignore the random variations in the manufacturing process, simulation-based design essentially becomes useless, since its predictions will be far from the reality of manufactured ICs. On the other hand, using design margins based on some traditional notion of worst-case scenarios can force us to sacri?ce too much in terms of power consumption or manufacturing cost, to the extent of making the design goals even infeasible. We absolutely need to explicitly account for the statistics of this random variability, to have design margins that are accurate so that we can ?nd the optimum balance between yield loss and design cost. This discontinuity in design processes has led many researchers to develop effective methods of statistical design, where the designer can simulate not just the behavior of the nominal design, but the expected statistics of the behavior in manufactured ICs. Memory circuits tend to be the hardest hit by the problem of these random variations because of their high replication count on any single chip, which demands a very high statistical quality from the product. Requirements of 5–6s (0.
Includes a treatment of memory design from the perspective of statistical analysis Covers relevant theoretical background from other fields: statistics, machine learning, optimization, reliability Explains the problem of estimating statistics of memory performance variation Shows solutions recently proposed in the Electronic Design Automation (EDA) community Contains chapters contributed from both industry and academia Includes supplementary material: sn.pub/extras
Autor*in
Amith Singhee
Themen in »Extreme Statistics in Nanoscale Memory Design«
CMOS Device Variability Modeling EVT Extreme Value Theory Memory Design Nanoscale VLSI Sampling-Based Estimation VLSI design automation electronic design automation integrated circuit material