High Energy Efficiency Neural Network Processor with Combined Digital and Computing-in-Memory Architecture
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Beschreibung
Neural network (NN) algorithms are driving the rapid development of modern artificial intelligence (AI). The energy-efficient NN processor has become an urgent requirement for the practical NN applications on widespread low-power AI devices. To address this challenge, this dissertation investigates pure-digital and digital computing-in-memory (digital-CIM) solutions and carries out four major studies.
For pure-digital NN processors, this book analyses the insufficient data reuse in conventional architectures and proposes a kernel-optimized NN processor. This dissertation adopts a structural frequency-domain compression algorithm, named CirCNN. The fabricated processor shows 8.1x/4.2x area/energy efficiency compared to the state-of-the-art NN processor. For digital-CIM NN processors, this dissertation combines the flexibility of digital circuits with the high energy efficiency of CIM. The fabricated CIM processor validates the sparsity improvement of the CIM architecture for the first time. This dissertation further designs a processor that considers the weight updating problem on the CIM architecture for the first time.
This dissertation demonstrates that the combination of digital and CIM circuits is a promising technical route for an energy-efficient NN processor, which can promote the large-scale application of low-power AI devices.
Neural network (NN) algorithms are driving the rapid development of modern artificial intelligence (AI). The energy-efficient NN processor has become an urgent requirement for the practical NN applications on widespread low-power AI devices. To address this challenge, this dissertation investigates pure-digital and digital computing-in-memory (digital-CIM) solutions and carries out four major studies.
For pure-digital NN processors, this book analyses the insufficient data reuse in conventional architectures and proposes a kernel-optimized NN processor. This dissertation adopts a structural frequency-domain compression algorithm, named CirCNN. The fabricated processor shows 8.1x/4.2x area/energy efficiency compared to the state-of-the-art NN processor. For digital-CIM NN processors, this dissertation combines the flexibility of digital circuits with the high energy efficiency of CIM. The fabricated CIM processor validates the sparsity improvement of the CIM architecture for the first time. This dissertation further designs a processor that considers the weight updating problem on the CIM architecture for the first time.
This dissertation demonstrates that the combination of digital and CIM circuits is a promising technical route for an energy-efficient NN processor, which can promote the large-scale application of low-power AI devices.
Nominated by the Tsinghua University as an outstanding Ph.D. thesis Introduces digital and computing-in-memory routes, and their combination for energy-efficient neural network processors Publishes partial results of this dissertation on the top journals/conferences (JSSC/ISSCC) in solid-state circuit field
Autor*in
Jinshan Yue
Themen in »High Energy Efficiency Neural Network Processor with Combined Digital and Computing-in-Memory Architecture«
Neural Network Processor High Energy Efficiency Application Specific Integrated Circuits Computing-in-Memory System on Chip