This book discloses the key points to achieve successful standard cell synthesis, from concept to implementation, that is not found in any other books. Standard cell library is the primitive level in the chip design flow and has significant impact on chip performance and the required time for design closure. However, most books of physical design field introduce standard cell design little. Design section describes the important measure of standard cells such as power performance and area and how to achieve better power performance area in standard cell design. To achieve this, this book starts from basics of transistor characteristics and extend to delay and power of standard cells.
The reader can not only learn the fundamental knowledge and algorithms to make up a standard cell synthesis tool, but also can know the indispensable techniques to realize a practical standard cell synthesis tool that is capable of optimizing the delay, area, pin accessibility, and coupling capacitance of cell layouts. Especially, how to systematically utilize the special M0 layer, which is only available in the nanometer-scale advanced technology nodes and has rarely been systematically discussed how to be applied to cell layout synthesis, is also disclosed in the book.
Yih-Lang Li
Transistor Placement Routing Planning Coupling-Capacitance Optimization Pin Accessibility Concurrent Routing