Semiconductor Advanced Packaging
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Beschreibung
The book focuses on the design, materials, process, fabrication, and reliability of advanced semiconductor packaging components and systems. Both principles and engineering practice have been addressed, with more weight placed on engineering practice. This is achieved by providing in-depth study on a number of major topics such as system-in-package, fan-in wafer/panel-level chip-scale packages, fan-out wafer/panel-level packaging, 2D, 2.1D, 2.3D, 2.5D, and 3D IC integration, chiplets packaging, chip-to-wafer bonding, wafer-to-wafer bonding, hybrid bonding, and dielectric materials for high speed and frequency. The book can benefit researchers, engineers, and graduate students in fields of electrical engineering, mechanical engineering, materials sciences, and industry engineering, etc.
The book focuses on the design, materials, process, fabrication, and reliability of advanced semiconductor packaging components and systems. Both principles and engineering practice have been addressed, with more weight placed on engineering practice. This is achieved by providing in-depth study on a number of major topics such as system-in-package, fan-in wafer/panel-level chip-scale packages, fan-out wafer/panel-level packaging, 2D, 2.1D, 2.3D, 2.5D, and 3D IC integration, chiplets packaging, chip-to-wafer bonding, wafer-to-wafer bonding, hybrid bonding, and dielectric materials for high speed and frequency. The book can benefit researchers, engineers, and graduate students in fields of electrical engineering, mechanical engineering, materials sciences, and industry engineering, etc.
Addresses advanced semiconductor packaging both in theory and practice Comprehensively studies design, materials, process, fabrication, and reliability of various advanced semiconductor packaging technologies Provides in-depth treatment of packaging technologies
Autor*in
John H. Lau
Themen in »Semiconductor Advanced Packaging«
System-in-Package Flip Chip Technology Thermocompression Bonding and Chip-to-Wafer Bonding Wafer-to-Wafer Bondind and Hybrid Bonding Fan-in Wafer/Panel-Level Chip-Scale Package Fan-out Wafer/Panel-Level Packaging Through-silicon Vias and Redistribution-Layers 2D, 2.1D, 2.3D, 2.5D, and 3D IC Integration High Bandwidth Memeory Heterogenenous Chiplets Integration