High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip
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Beschreibung
This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures.
This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures.
Offers a systematic approach to high-level reliability estimation and exploration Presents step-by-step procedures for 11 novel techniques and solutions Includes more than 100 figures and illustrations Includes supplementary material: sn.pub/extras
Autor*in
Zheng Wang
Themen in »High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip«
Architectural Reliability Estimation System- Level Reliability Exploration Architectural Fault Tolerance Processor Design Asymmetric Reliability System-Level Design Probabilistic Error Masking Matrix (PeMM) Node Fault Tolerance (NFT) Reliability Task Mapping Statistical Error Confinement