VLSI Physical Design: From Graph Partitioning to Timing Closure
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Beschreibung
Design and optimization of integrated circuits are essential to the creation of new semiconductor chips, and physical optimizations are becoming more prominent as a result of semiconductor scaling. Modern chip design has become so complex that it is largely performed by specialized software, which is frequently updated to address advances in semiconductor technologies and increased problem complexities. A user of such software needs a high-level understanding of the underlying mathematical models and algorithms. On the other hand, a developer of such software must have a keen understanding of computer science aspects, including algorithmic performance bottlenecks and how various algorithms operate and interact.
"VLSI Physical Design: From Graph Partitioning to Timing Closure"
introduces and compares algorithms that are used during the physical design phase of integrated-circuit design, wherein a geometric chip layout is produced starting from an abstract circuit design. The emphasis is on essential and fundamental techniques, ranging from hypergraph partitioning and circuit placement to timing closure.
For Slides and Other Information: https://www.ifte.de/books/eda/index.html
Design and optimization of integrated circuits are essential to the creation of new semiconductor chips, and physical optimizations are becoming more prominent as a result of semiconductor scaling. Modern chip design has become so complex that it is largely performed by specialized software, which is frequently updated to address advances in semiconductor technologies and increased problem complexities. A user of such software needs a high-level understanding of the underlying mathematical models and algorithms. On the other hand, a developer of such software must have a keen understanding of computer science aspects, including algorithmic performance bottlenecks and how various algorithms operate and interact.
"VLSI Physical Design: From Graph Partitioning to Timing Closure"
introduces and compares algorithms that are used during the physical design phase of integrated-circuit design, wherein a geometric chip layout is produced starting from an abstract circuit design. The emphasis is on essential and fundamental techniques, ranging from hypergraph partitioning and circuit placement to timing closure.Comprehensive coverage of physical design of integrated circuits, PCBs and MCMs, with emphasis on practical algorithms and methodologies
A chapter on timing closure that includes a discussion of design flows
Detailed illustrations of key concepts, numerous examples
Brief surveys of recent research results with up-to-date references for further reading
Accessible to beginners and students
Problem sets for students, with solutions
Includes supplementary material: sn.pub/extras
Autor*in
Andrew B. Kahng
Themen in »VLSI Physical Design: From Graph Partitioning to Timing Closure«
EDA Electronic Design Automation Electronics Physical design algorithms VLSI design chip planning design automation partitioning placement routing time closure
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