Sigma Delta A/D Conversion for Signal Conditioning
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Beschreibung
1.1 Background Moore’s Law predicts a decrease by a factor of two in the feature size of CMOS te- nology every three years and has been valid for years. It implies a doubling of the - eration speed and a four times higher transistor count per unit of area, every three years. The combination leads to an eight times higher processing capability per unit of area. This on-going miniaturization allows the integration of complex electronic systems with millions of transistors (Very-Large-Scale-Integration) and enables the integration of el- tronic systems. An electronic system A generic picture of an integrated electronic system is shown in ?g. 1.1. The heart of the system is the signal processing core. This core supports a wide variety of functions, such as customization and programmability of multiple applications, channel coding, the de?nition of the user interface, etc. These functions are enabled by DSP, a controller CPU and various blocks of memory. In advanced ICs these blocks provide (almost) all signal processing and usually dominate in the overall power and area consumption of integrated systems. The huge data rates involved, require high-speed busses for communication between these blocks. A power-management unit fuels the system by providing the - propriate supply voltages and currents.
Provides an accessible overview of the state-of-the-art in sigma-delta converter design Derives the power/performance relation of both the sigma-delta converter and the decimation filter Analyzes the various aspects of the interferer-immunity of a continuous-time sigma-delta converter Presents advanced sigma-delta topologies with improved interferer-immunity Studies the sigma-delta converter within a receiver application and presents an alternative highly-digital receiver with signal conditioning integrated into the sigma-delta converter
Autor*in
Kathleen Philips
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