Models in Hardware Testing
Lecture Notes of the Forum in Honor of Christian Landrault
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Beschreibung
Model based testing is the most powerful technique for testing hardware and software systems. Models in Hardware Testing describes the use of models at all the levels of hardware testing. The relevant fault models for nanoscaled CMOS technology are introduced, and their implications on fault simulation, automatic test pattern generation, fault diagnosis, memory testing and power aware testing are discussed. Models and the corresponding algorithms are considered with respect to the most recent state of the art, and they are put into a historical context by a concluding chapter on the use of physical fault models in fault tolerance.
Models in Hardware Testing treats models and especially fault models in hardware testing in a comprehensive way not found anywhere else. Engineers who are responsible for product quality and test coverage, students who want to learn about quality assessment for new technologies or lecturers who are interested in the most recent advances in model based hardware testing will take benefits from reading.
The material collected in Models in Hardware Testing was prepared for the forum in honor of Christian Landrault in connection with the European Test Symposium 2009.
Model based testing is the most powerful technique for testing hardware and software systems. Models in Hardware Testing describes the use of models at all the levels of hardware testing. The relevant fault models for nanoscaled CMOS technology are introduced, and their implications on fault simulation, automatic test pattern generation, fault diagnosis, memory testing and power aware testing are discussed. Models and the corresponding algorithms are considered with respect to the most recent state of the art, and they are put into a historical context by a concluding chapter on the use of physical fault models in fault tolerance.
Introduction of model based hardware testing Describes fault models for nanoscaled CMOS technology Fault simulation, ATPG and diagnosis algorithms for complex fault models Comprehensive treatment including memory and low power aspects
Autor*in
Hans-Joachim Wunderlich
Themen in »Models in Hardware Testing«
Automat CMOS Hardware algorithms logic model modeling simulation