On Memory Systems in Parallel Architectures
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Beschreibung
Memory is the major bottleneck in contemporary processors as its technology scaling keeps lagging behind logic cells. To address this challenge, computer architects have resorted to various parallel archictectures. These archictectures still contain a memory system that needs to be optimized for parallel processing. This thesis first portrays the shift to parallel architectures and how they address the limitations of sequential single-core processors. Out-of-order processors find instructions that can be executed in parallel at runtime. Vector instruction set architectures encode parallelism in the insruction word itself at compile time. Multi-processor systems-on-a-chip (MPSoCs) execute entire instruction threads in parallel. The latter two are more energy-efficient and preferable where applicable. We demonstrate at the example of communications signal processing for current and next-generation radio access networks the strengths and limitations of vector processors and MPSoCs. Based on the analysis, we argue for a heterogeneous MPSoC as a fabric for flexible and scalable communications signal processing platforms. This MPSoC contains general-purpose processors, vector processors, accelerators, and a shared memory system. In the second part of the thesis, we optimize the different components of this vision. We first take a look at the shared memory system and the conflicts it entails. We opt for access interval prediction as a means to manage the timing impact of conflict arbitration. Drawing inspiration from branch prediction, we derive, optimize and implement an access interval predictor with an accuracy of 97 % outperforming other implementable predictors found in literature. The next optimization regards the access pattern of vector processors on the main memory. In certain situations, which we analyze thoroughly, it is beneficial to load two vectors in parallel. Dual load can boost the performance of vector processors up to 33 % and we demonstrate a gain of 21 % at an area increase of less than 2 % in a proof of concept. Finally, we take a look inside the vector processor, where we can find a small shared memory system, as well. The vector register file architecture needs to avoid, resolve, and mitigate access conflicts. We examine the conflicts and propose dynamic bank layout and an improved arbitration as an alternative to area-expensive deep operand queues for conflict management at no runtime impact or even a slight improvement.
Autor*in
Viktor Razilov