Timing Model Derivation

Beschreibung

Safety-critical hard real-time systems are subject to strict timing constraints...
Safety-critical hard real-time systems are subject to strict timing constraints. In order to derive guarantees on the timing behavior, the worst-case execution time (WCET) of each task comprising the system has to be known. The aiT tool has been developed for computing safe upper bounds on the WCET of a task. Its computation is mainly based on abstract interpretation of timing models of the processor and its periphery. These models are currently hand-crafted by human experts, which is a time-consuming and error-prone process. Modern processors are automatically synthesized from formal hardware specifications. Besides the processor’s functional behavior, also timing aspects are included in these descriptions. A methodology to derive sound timing models using hardware specifications is described within this thesis. To ease the process of timing model derivation, the methodology is embedded into a sound framework. A key part of this framework are static analyses on hardware specifications. This thesis presents an analysis framework that is build on the theory of abstract interpretation allowing use of classical program analyses on hardware description languages. Its suitability to automate parts of the derivation methodology is shown by different analyses. Practical experiments demonstrate the applicability of the approach to derive timing models. Also the soundness of the analyses and the analyses’ results is proved.

Autor*in

Marc Schlickling
Studium der Informatik an der Universität des Saarlandes. Seit 2005 angestellt bei der AbsInt GmbH in Saarbrücken. Promotion an der Universität des Saarlandes in 2012.

Themen in »Timing Model Derivation«

WCET VHDL static analysis abstract interpretation data-flow analysis

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