Automatic Analog Layout Synthesis – from Capacitor Arrays in Data Converters to General Design with Routing

Beschreibung

Ratioed capacitor arrays exist in various analog circuits such as data converters. The mismatch of ratio affects the linearity of the circuit output. Moreover, capacitors often consume the majority of the layout area. Therefore, mismatch and area reduction are two key objectives of capacitor array layout optimization. For this task, two deterministic approaches are introduced, followed by a stochastic approach using metal-oxide-metal capacitors. Lastly, a layout representation based on sequence pair is proposed to realize simultaneous placement and routing for analog layout synthesis.

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Pang-Yen Chou

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analog layout automation

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