Virtual ESD Test –

Beschreibung

Electrostatic discharge (ESD) protection of integrated circuits can be analyzed and optimized at chip level already in an early product development phase with the methodology presented in this work. The technique which was developed is modeling the IC including the package, controls simulation steps and evaluates simulation results in order to detect and identify critical human body model (HBM) stress events. The simulation is based on a behavioral model, which enables the analysis of all possible discharge paths through the chip. The presented measurement technique which determines the current and voltage distribution on an IC during a high current pulse can be applied for parameterization and verification of the simulation method. One of the successfully applied analysis was a product failure combined with the optimization of the protection concept.

Autor*in

Stephan Drüen

Themen in »Virtual ESD Test –«

Chip Level ESD ESD Simulation Methodology Elektrotechnik Halbleiterelektronik Simulation

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