Practical Formal Methods for Hardware Design
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Beschreibung
Formal methods for hardware design still find limited use in industry. Yet current practice has to change to cope with decreasing design times and increasing quality requirements. This research report presents results from the Esprit project FORMAT (formal methods in hardware verification) which involved the collaboration of the enterprises Siemens, Italtel, Telefonica I+D, TGI, and AHL, the research institute OFFIS, and the universities of Madrid and Passau. The work presented involves advanced specification languages for hardware design that are intuitive to the designer, like timing diagrams and state based languages, as well as their relation to VHDL and formal languages like temporal logic and a process-algebraic calculus. The results of experimental tests of the tools are also presented.
This Esprit volume presents research results from the FORMAT (formal methods in hardware verification) project, a collaboration of five European enterprises, a research institute, and two universities.
Autor*in
Carlos Delgado Kloos
Themen in »Practical Formal Methods for Hardware Design«
Design aids Entwurfswerkezeuge Formal models Hardware description languages Hardware-Beschreibungssprachen Mechanical verfication Mechanische Verifikation Specification techniques Spezifikationstechniken VHDL VLSI formal verification verification