Architecture Design and Validation Methods
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Beschreibung
This book grew out of material which was taught at the International Summer School on Architecture Design and Validation Methods, held June 23-July 5, 1997, on the Island of Lipari and directed to graduate students and young researchers. Since then the course notes have been completely elaborated and extended and additional chapters have been added so that this book offers a comprehensive presentation of the state of the art which leads the reader to the forefront of the current research in the area. The chapters, each of which was written by a group of eminent special ists in the field, are self-contained and can be read independently of each other. They cover the wide range of theoretical and practical methods which currently used for the specification, design, validation and verification of are hardware/software architectures. Synthesis methods are the subject of the first three chapters. The chapter on Modeling and Synthesis of Behavior, Control and Data Flow focusses on techniques above the register-transfer level. The chapter on Cell-Based Logic Optimizations concentrates on methods that interface logic design with phys ical design, in particular on techniques for cell-library binding, the back-end of logic synthesis. The chapter on A Design Flow for Performance Planning presents new paradigms for iteration-free synthesis where global wire plans for meeting timing constraints already appear at the conceptual design stage, even before fixing the functionality of the blocks in the plan.
Comprehensive state-of-the-art survey of design and validation of computer architectures Systematic coverage providing a clear vision of the problems and advanced techniques for their solution Seven chapters by eminent researchers presuppose only basic knowledge and lead to the forefront of research Includes supplementary material: sn.pub/extras
Autor*in
Egon Börger
Themen in »Architecture Design and Validation Methods«
Design of computer architectures Design von Rechnerarchitekturen Modeling and behav ioral synthesis Modellierung und Synthese Rechnerarchitektur Testability Testbarkeit Validation of computer architectures Validier computer computer architecture