This Esprit volume presents research results from the FORMAT (formal methods in hardware verification) project, a collaboration of five European enterprises, a research institute, and two universities.
Carlos Delgado Kloos
Design aids Entwurfswerkezeuge Formal models Hardware description languages Hardware-Beschreibungssprachen Mechanical verfication Mechanische Verifikation Specification techniques Spezifikationstechniken VHDL VLSI formal verification verification