System Level Design from HW/SW to Memory for Embedded Systems

Beschreibung

This book constitutes the refereed proceedings of the 5th IFIP TC 10 International Embedded Systems Symposium, IESS 2015, held in Foz do Iguaçu, Brazil, in November 2015.

The 18 full revised papers presented were carefully reviewed and selected from 25 submissions. The papers present a broad discussion on the design, analysis and verification of embedded and cyber-physical systems including design methodologies, verification, performance analysis, and real-time systems design. They are organized in the following topical sections: cyber-physical systems, system-level design; multi/many-core system design; memory system design; and embedded HW/SW design and applications.

Autor*in

Marcelo Götz

Themen in »System Level Design from HW/SW to Memory for Embedded Systems«

applied computing bandwidth computer architecture cyber-physical systems embedded systems Field Programmable Gate Array (FPGA) image processing microprocessor chips many-core systems model checking multicore systems semantics software engineering specifications verification

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