Timing Performance of Nanometer Digital Circuits Under Process Variations
Buch in deiner Nähe kaufen
Beschreibung
This book discusses the digital design of integrated circuits under process variations, with a focus on design-time solutions. The authors describe a step-by-step methodology, going from logic gates to logic paths to the circuit level. Topics are presented in comprehensively, without overwhelming use of analytical formulations. Emphasis is placed on providing digital designers with understanding of the sources of process variations, their impact on circuit performance and tools for improving their designs to comply with product specifications. Various circuit-level “design hints” are highlighted, so that readers can use then to improve their designs. A special treatment is devoted to unique design issues and the impact of process variations on the performance of FinFET based circuits. This book enables readers to make optimal decisions at design time, toward more efficient circuits, with better yield and higher reliability.
This book discusses the digital design of integrated circuits under process variations, with a focus on design-time solutions. The authors describe a step-by-step methodology, going from logic gates to logic paths to the circuit level. Topics are presented in comprehensively, without overwhelming use of analytical formulations. Emphasis is placed on providing digital designers with understanding of the sources of process variations, their impact on circuit performance and tools for improving their designs to comply with product specifications. Various circuit-level “design hints” are highlighted, so that readers can use then to improve their designs. A special treatment is devoted to unique design issues and the impact of process variations on the performance of FinFET based circuits. This book enables readers to make optimal decisions at design time, toward more efficient circuits, with better yield and higher reliability.
Describes in detail the digital design of integrated circuit under process variations with a focus on design-time understanding and optimization Follows a step-by-step sequence in methodology, going from logic gates to logic paths to circuit level, in order to explain the behavior of process variations at the different levels of abstraction Presents novel design issues for FinFET based digital circuits Provides step-by-step examples of quantitative estimation of the timing performance of logic cells and logic paths, as well as a comparison with Spice simulation results
Autor*in
Victor Champac
Themen in »Timing Performance of Nanometer Digital Circuits Under Process Variations«
Process Variations and Probabilistic Integrated Circuit Design Variation-Aware Design of Custom Integrated Circuits Statistical Performance Modeling and Optimization Yield and Variability Optimization of Integrated Circuits Statistical Analysis and Optimization for VLSI