Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip
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Beschreibung
This book pioneers the field of gain-cell embedded DRAM (GC-eDRAM) design for low-power VLSI systems-on-chip (SoCs). Novel GC-eDRAMs are specifically designed and optimized for a range of low-power VLSI SoCs, ranging from ultra-low power to power-aware high-performance applications. After a detailed review of prior-art GC-eDRAMs, an analytical retention time distribution model is introduced and validated by silicon measurements, which is key for low-power GC-eDRAM design. The book then investigates supply voltage scaling and near-threshold voltage (NTV) operation of a conventional gain cell (GC), before presenting novel GC circuit and assist techniques for NTV operation, including a 3-transistor full transmission-gate write port, reverse body biasing (RBB), and a replica technique for optimum refresh timing. Next, conventional GC bitcells are evaluated under aggressive technology and voltage scaling (down to the subthreshold domain), before novel bitcells for aggressively scaled CMOS nodes and soft-error tolerance as presented, including a 4-transistor GC with partial internal feedback and a 4-transistor GC with built-in redundancy.
This book pioneers the field of gain-cell embedded DRAM (GC-eDRAM) design for low-power VLSI systems-on-chip (SoCs). Novel GC-eDRAMs are specifically designed and optimized for a range of low-power VLSI SoCs, ranging from ultra-low power to power-aware high-performance applications. After a detailed review of prior-art GC-eDRAMs, an analytical retention time distribution model is introduced and validated by silicon measurements, which is key for low-power GC-eDRAM design. The book then investigates supply voltage scaling and near-threshold voltage (NTV) operation of a conventional gain cell (GC), before presenting novel GC circuit and assist techniques for NTV operation, including a 3-transistor full transmission-gate write port, reverse body biasing (RBB), and a replica technique for optimum refresh timing. Next, conventional GC bitcells are evaluated under aggressive technology and voltage scaling (down to the subthreshold domain), before novel bitcells for aggressively scaled CMOS nodes and soft-error tolerance as presented, including a 4-transistor GC with partial internal feedback and a 4-transistor GC with built-in redundancy.
Provides novel gain-cell embedded DRAM (GC-eDRAM) designs for various low-power VLSI SoC applications; Models the statistical retention time distribution of GC-eDRAM and validates the model by silicon measurements; Describes various memory optimizations, including unique bitcell and assist circuits, targeted at increased retention time and reduced power consumption while hardly compromising area and speed; Demonstrates several new techniques at the circuit, architectural, and algorithmic levels which enable NTV and subthreshold operation of GC-eDRAM, implementation of GC-eDRAM in aggressively scaled CMOS nodes, as well as soft-error tolerance. Includes supplementary material: sn.pub/extras
Autor*in
Pascal Meinerzhagen
Themen in »Gain-Cell Embedded DRAMs for Low-Power VLSI Systems-on-Chip«
Memory Systems Memory for VLSI embedded DRAM memory embedded memory design memory optimization error-tolerant embedded memory