Electromigration Inside Logic Cells
Modeling, Analyzing and Mitigating Signal Electromigration in NanoCMOS
Buch in deiner Nähe kaufen
Beschreibung
This book describes new and effective methodologies for modeling, analyzing and mitigating cell-internal signal electromigration in nanoCMOS, with significant circuit lifetime improvements and no impact on performance, area and power. The authors are the first to analyze and propose a solution for the electromigration effects inside logic cells of a circuit. They show in this book that an interconnect inside a cell can fail reducing considerably the circuit lifetime and they demonstrate a methodology to optimize the lifetime of circuits, by placing the output, Vdd and Vss pin of the cells in the less critical regions, where the electromigration effects are reduced. Readers will be enabled to apply this methodology only for the critical cells in the circuit, avoiding impact in the circuit delay, area and performance, thus increasing the lifetime of the circuit without loss in other characteristics.
This book describes new and effective methodologies for modeling, analyzing and mitigating cell-internal signal electromigration in nanoCMOS, with significant circuit lifetime improvements and no impact on performance, area and power. The authors are the first to analyze and propose a solution for the electromigration effects inside logic cells of a circuit. They show in this book that an interconnect inside a cell can fail reducing considerably the circuit lifetime and they demonstrate a methodology to optimize the lifetime of circuits, by placing the output, Vdd and Vss pin of the cells in the less critical regions, where the electromigration effects are reduced. Readers will be enabled to apply this methodology only for the critical cells in the circuit, avoiding impact in the circuit delay, area and performance, thus increasing the lifetime of the circuit without loss in other characteristics.
Provides a comprehensive overview of signal electromigration analysis and modeling within logic cells, along with mitigation methodologies Presents an algorithm to optimize the lifetime of circuits by cell pin placement Describes a full circuit design flow, incorporating the electromigration mitigation methodologies demonstrated in this book
Autor*in
Gracieli Posser
Themen in »Electromigration Inside Logic Cells«
Circuit reliability Electromigration Techniques Electromigration Modeling cell-internal signal electromigration cell-internal electromigration at 22nm