Noise-Shaping All-Digital Phase-Locked Loops
Modeling, Simulation, Analysis and Design
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Beschreibung
This book presents a novel approach to the analysis and design of all-digital phase-locked loops (ADPLLs), technology widely used in wireless communication devices. The authors provide an overview of ADPLL architectures, time-to-digital converters (TDCs) and noise shaping. Realistic examples illustrate how to analyze and simulate phase noise in the presence of sigma-delta modulation and time-to-digital conversion. Readers will gain a deep understanding of ADPLLs and the central role played by noise-shaping. A range of ADPLL and TDC architectures are presented in unified manner. Analytical and simulation tools are discussed in detail. Matlab code is included that can be reused to design, simulate and analyze the ADPLL architectures that are presented in the book.
• Discusses in detail a wide range of all-digital phase-locked loops architectures;
• Presents a unified framework in which to model time-to-digital converters for ADPLLs;
• Explains a procedure to predict and simulate phase noise in oscillators and ADPLLs;
• Describes an efficient approach to model ADPLLS;
• Includes Matlab code to reproduce the examples in the book.
This book presents a novel approach to the analysis and design of all-digital phase-locked loops (ADPLLs), technology widely used in wireless communication devices. The authors provide an overview of ADPLL architectures, time-to-digital converters (TDCs) and noise shaping. Realistic examples illustrate how to analyze and simulate phase noise in the presence of sigma-delta modulation and time-to-digital conversion. Readers will gain a deep understanding of ADPLLs and the central role played by noise-shaping. A range of ADPLL and TDC architectures are presented in unified manner. Analytical and simulation tools are discussed in detail. Matlab code is included that can be reused to design, simulate and analyze the ADPLL architectures that are presented in the book.
Discusses in detail a wide range of all-digital phase-locked loops architectures Presents a unified framework in which to model time-to-digital converters for ADPLLs Explains a procedure to predict and simulate phase noise in oscillators and ADPLLs Describes an efficient approach to model ADPLLS Includes Simulink and Matlab code to reproduce the examples in the book Includes supplementary material: sn.pub/extras
Autor*in
Francesco Brandonisio
Themen in »Noise-Shaping All-Digital Phase-Locked Loops«
All-Digital Phase-Locked Loops Analog Circuits and Signal Processing Modeling All-Digital Phase-Locked Loops Noise Shaping and Dither Phase Noise in All-Digital Phase-Locked Loops Phase Noise in Oscillators Time-to-digital Converters