Memory Controllers for Mixed-Time-Criticality Systems
Architectures, Methodologies and Trade-offs
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Beschreibung
This book discusses the design and performance analysis of SDRAM controllers that cater to both real-time and best-effort applications, i.e. mixed-time-criticality memory controllers. The authors describe the state of the art, and then focus on an architecture template for reconfigurable memory controllers that addresses effectively the quickly evolving set of SDRAM standards, in terms of worst-case timing and power analysis, as well as implementation. A prototype implementation of the controller in SystemC and synthesizable VHDL for an FPGA development board are used as a proof of concept of the architecture template.
This book discusses the design and performance analysis of SDRAM controllers that cater to both real-time and best-effort applications, i.e. mixed-time-criticality memory controllers. The authors describe the state of the art, and then focus on an architecture template for reconfigurable memory controllers that addresses effectively the quickly evolving set of SDRAM standards, in terms of worst-case timing and power analysis, as well as implementation. A prototype implementation of the controller in SystemC and synthesizable VHDL for an FPGA development board are used as a proof of concept of the architecture template.
Discusses power-constrained mixed-time-criticality systems and why they are complex to design and verify Explains the concepts of predictability and composability and how they address the design and verification challenges of mixed-time-criticality systems Provides an overview of the requirements of memory controllers in power-constrained mixed-time-criticality systems and discusses why current memory controllers struggle to satisfy them Includes supplementary material: sn.pub/extras
Autor*in
Sven Goossens
Themen in »Memory Controllers for Mixed-Time-Criticality Systems«
Memory Controllers Memory Systems Memory Controllers for Real-Time Embedded Systems mixed-time-criticality memory controllers Reconfiguration in memory controllers Power/performance tradeoffs in memory controllers Mixed time criticaliity SDRAM