Silicon Nanowire Transistors
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Beschreibung
This book describes the n and p-channel Silicon Nanowire Transistor (SNT) designs with single and dual-work functions, emphasizing low static and dynamic power consumption. The authors describe a process flow for fabrication and generate SPICE models for building various digital and analog circuits. These include an SRAM, a baseband spread spectrum transmitter, a neuron cell and a Field Programmable Gate Array (FPGA) platform in the digital domain, as well as high bandwidth single-stage and operational amplifiers, RF communication circuits in the analog domain, in order to show this technology’s true potential for the next generation VLSI.
- Describes Silicon Nanowire (SNW) Transistors, as vertically constructed MOS n and p-channel transistors, with low static and dynamic power consumption and small layout footprint;
- Targets System-on-Chip (SoC) design, supporting very high transistor count (ULSI), minimal powerconsumption requiring inexpensive substrates for packaging;
- Enables fabrication of different types of memory on the same chip, such as capacitive cells and transistors with floating gates that can be used as DRAMs and Flash memories.
This book describes the n and p-channel Silicon Nanowire Transistor (SNT) designs with single and dual-work functions, emphasizing low static and dynamic power consumption. The authors describe a process flow for fabrication and generate SPICE models for building various digital and analog circuits. These include an SRAM, a baseband spread spectrum transmitter, a neuron cell and a Field Programmable Gate Array (FPGA) platform in the digital domain, as well as high bandwidth single-stage and operational amplifiers, RF communication circuits in the analog domain, in order to show this technology’s true potential for the next generation VLSI.
Describes Silicon Nanowire (SNW) Transistors, as vertically constructed MOS n and p-channel transistors, with low static and dynamic power consumption and small layout footprint; Targets System-on-Chip (SoC) design, supporting very high transistor count (ULSI), minimal power consumption requiring inexpensive substrates for packaging; Enables fabrication of different types of memory on the same chip, such as capacitive cells and transistors with floating gates that can be used as DRAMs and Flash memories. Includes supplementary material: sn.pub/extras
Autor*in
Ahmet Bindal
Themen in »Silicon Nanowire Transistors«
Carbon Nanotubes Hybrid Memory Design NMOS Transistors Silicon Nanowire Silicon Nanowire Transistors System-on-Chip Design and Packaging Ultra large scale Integration