A Pipelined Multi-core MIPS Machine
Hardware Implementation and Correctness Proof
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Beschreibung
This monograph is based on the third author's lectures on computer architecture, given in the summer semester 2013 at Saarland University, Germany. It contains a gate level construction of a multi-core machine with pipelined MIPS processor cores and a sequentially consistent shared memory.
The book contains the first correctness proofs for both the gate level implementation of a multi-core processor and also of a cache based sequentially consistent shared memory. This opens the way to the formal verification of synthesizable hardware for multi-core processors in the future.
Constructions are in a gate level hardware model and thus deterministic. In contrast the reference models against which correctness is shown are nondeterministic. The development of the additional machinery for these proofs and the correctness proof of the shared memory at the gate level are the main technical contributions of this work.
Demonstrates construction of a multi-core machine with pipelined MIPS processor Broadens the understanding of RISC machines Opens the way to the formal verification of synthesizable hardware for multi-core processors
Autor*in
Mikhail Kovalev
Themen in »A Pipelined Multi-core MIPS Machine«
algebraic specification arithmetic logic unit automata states basic pipelined processor design basic sequential mips machine cache protocol automata finite state machines instruction set architecture memory embedding microprocessor without interlocked pipeline stages multi-bank ram multi-core next pc environment pipelining scheduling functions