This book presents a comprehensive, academically rigorous, and industry-grounded framework for modeling power and performance in modern CPUs and GPUs. It bridges architectural theory, workload-driven performance analysis, and realistic chip-level power modeling, explicitly incorporating variations and constraints that are often treated as secondary or external—such as thermals, yield, reliability, and power delivery. By integrating these dimensions into a single framework, the book connects early architectural decisions to post-silicon behavior and manufacturing out-comes, and demonstrates how accurate power–performance (PnP) modeling can directly inform high-impact decisions including binning strategy, product stacking, and wafer utilization.
This book presents a comprehensive, academically rigorous, and industry-grounded framework for modeling power and performance in modern CPUs and GPUs. It bridges architectural theory, workload-driven performance analysis, and realistic chip-level power modeling, explicitly incorporating variations and constraints that are often treated as secondary or external—such as thermals, yield, reliability, and power delivery. By integrating these dimensions into a single framework, the book connects early architectural decisions to post-silicon behavior and manufacturing out-comes, and demonstrates how accurate power–performance (PnP) modeling can directly inform high-impact decisions including binning strategy, product stacking, and wafer utilization.
Rany Elsayed
Computer Architecture Performance per Cycle Power Modeling GPU Power and Performance Modeling Power–Performance (PnP) Modeling CPU Power and Performance Modeling System-on-Chip (SoC) Modeling