On-Chip Training NPU - Algorithm, Architecture and SoC Design
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Beschreibung
Unlike most available sources that focus on deep neural network (DNN) inference, this book provides readers with a single-source reference on the needs, requirements, and challenges involved with on-device, DNN training semiconductor and SoC design. The authors include coverage of the trends and history surrounding the development of on-device DNN training, as well as on-device training semiconductors and SoC design examples to facilitate understanding.
- Focuses on the requirements and challenges of on-device deep neural network (DNN) training, rather than DNN inference;
- Provides guidelines for on-device, DNN training semiconductor or System-on-Chip (SoC) design;
- Includes on-device training semiconductors and SoC design examples to facilitate understanding
Unlike most available sources that focus on deep neural network (DNN) inference, this book provides readers with a single-source reference on the needs, requirements, and challenges involved with on-device, DNN training semiconductor and SoC design. The authors include coverage of the trends and history surrounding the development of on-device DNN training, as well as on-device training semiconductors and SoC design examples to facilitate understanding.
Focuses on the requirements and challenges of on-device deep neural network (DNN) training, rather than DNN inference Provides guidelines for on-device, DNN training semiconductor or system-on-chip (SoC) design Includes on-device training semiconductors and SoC design examples to facilitate understanding
Autor*in
Donghyeon Han
Themen in »On-Chip Training NPU - Algorithm, Architecture and SoC Design«
AI Semiconductor AI SoC Artificial intelligence Deep neural network On-device DNN training