Efficient Execution of Irregular Dataflow Graphs
Hardware/Software Co-optimization for Probabilistic AI and Sparse Linear Algebra
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Beschreibung
This book focuses on the acceleration of emerging irregular sparse workloads, posed by novel artificial intelligent (AI) models and sparse linear algebra. Specifically, the book outlines several co-optimized hardware-software solutions for a highly promising class of emerging sparse AI models called Probabilistic Circuit (PC) and a similar sparse matrix workload for triangular linear systems (SpTRSV). The authors describe optimizations for the entire stack, targeting applications, compilation, hardware architecture and silicon implementation, resulting in orders of magnitude higher performance and energy-efficiency compared to the existing state-of-the-art solutions. Thus, this book provides important building blocks for the upcoming generation of edge AI platforms.
- Analyzes the key bottlenecks in the existing platforms for these sparse and irregular AI and linear algebra algorithms;
- Discusses an emerging set of AI workloads that rely on sparse matrix operations andgraph-based computations;
- Shows how to address the execution challenges of this novel class of algorithms through hardware-software codesign.
This book focuses on the acceleration of emerging irregular sparse workloads, posed by novel artificial intelligent (AI) models and sparse linear algebra. Specifically, the book outlines several co-optimized hardware-software solutions for a highly promising class of emerging sparse AI models called Probabilistic Circuit (PC) and a similar sparse matrix workload for triangular linear systems (SpTRSV). The authors describe optimizations for the entire stack, targeting applications, compilation, hardware architecture and silicon implementation, resulting in orders of magnitude higher performance and energy-efficiency compared to the existing state-of-the-art solutions. Thus, this book provides important building blocks for the upcoming generation of edge AI platforms.
Analyzes the key bottlenecks in the existing platforms for these sparse and irregular AI and linear algebra algorithms; Discusses an emerging set of AI workloads that rely on sparse matrix operations and graph-based computations; Shows how to address the execution challenges of this novel class of algorithms through hardware-software codesign.
Autor*in
Nimish Shah
Themen in »Efficient Execution of Irregular Dataflow Graphs«
hardware for sparse matrix operations parallel computer architecture hardware for probabilistic inference hardware/software codesign Edge AI hardware for irregular graphs