Automated Analysis of Virtual Prototypes at the Electronic System Level
Design Understanding and Applications
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Beschreibung
This book describes a set of SystemC‐based virtual prototype analysis methodologies, including design understanding, verification, security validation, and design space exploration. Readers will gain an overview of the latest research results in the field of Electronic Design Automation (EDA) at the Electronic System Level (ESL). The methodologies discussed enable readers to tackle easily key tasks and applications in the design process.
- Provides an extensive introduction to the field of SystemC‐based virtual prototype (VP) analysis at the electronic system level;
- Describes a design understanding methodology from both debugger-based and compiler‐based perspectives;
- Illustrates a semi‐formal verification approach to check the validity of a given VP against its specification, user‐defined rules and protocol;
- Discusses a security validation approach to validate the run‐time behavior of a given VP-based SoC against security threat models, such as information leakage (confidentiality) and unauthorized access to data in a memory (integrity);
- Describes a design space exploration approach for SystemC-based VPs to guide designers to know under which error limits, different portions of a given VP can be approximated at different granularity levels.
This book describes a set of SystemC‐based virtual prototype analysis methodologies, including design understanding, verification, security validation, and design space exploration. Readers will gain an overview of the latest research results in the field of Electronic Design Automation (EDA) at the Electronic System Level (ESL). The methodologies discussed enable readers to tackle easily key tasks and applications in the design process.
Provides an extensive introduction to the field of SystemC-based virtual prototype (VP) analysis at the electronic system level Describes a design understanding methodology from both debugger-based and compiler-based perspectives Illustrates a semi-formal verification approach to check the validity of a given VP against its specification, user-defined rules and protocol Discusses a security validation approach to validate the run-time behavior of a given VP-based SoC against security threat models, such as information leakage (confidentiality) and unauthorized access to data in a memory (integrity) Describes a design space exploration approach for SystemC-based VPs to guide designers to know under which error limits, different portions of a given VP can be approximated at different granularity levels
Autor*in
Mehran Goli
Themen in »Automated Analysis of Virtual Prototypes at the Electronic System Level«
Electronic System Level Design Transaction Level Modeling Design space exploration Semi-formal verification SoC security threats