In-Memory Computing
Synthesis and Optimization
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Beschreibung
This book describes a comprehensive approach for synthesis and optimization of logic-in-memory computing hardware and architectures using memristive devices, which creates a firm foundation for practical applications. Readers will get familiar with a new generation of computer architectures that potentially can perform faster, as the necessity for communication between the processor and memory is surpassed. The discussion includes various synthesis methodologies and optimization algorithms targeting implementation cost metrics including latency and area overhead as well as the reliability issue caused by short memory lifetime.
- Presents a comprehensive synthesis flow for the emerging field of logic-in-memory computing;
- Describes automated compilation of programmable logic-in-memory computer architectures;
- Includes several effective optimization algorithm also applicable to classical logic synthesis;
- Investigates unbalanced write traffic in logic-in-memory architectures and describes wear leveling approaches to alleviate it.
This book describes a comprehensive approach for synthesis and optimization of logic-in-memory computing hardware and architectures using memristive devices, which creates a firm foundation for practical applications. Readers will get familiar with a new generation of computer architectures that potentially can perform faster, as the necessity for communication between the processor and memory is surpassed. The discussion includes various synthesis methodologies and optimization algorithms targeting implementation cost metrics including latency and area overhead as well as the reliability issue caused by short memory lifetime.
- Presents a comprehensive synthesis flow for the emerging field of logic-in-memory computing;
- Describes automated compilation of programmable logic-in-memory computer architectures;
- Includes several effective optimization algorithm also applicable to classical logic synthesis;
- Investigates unbalanced write traffic in logic-in-memory architectures and describes wear leveling approaches to alleviate it.
Presents a comprehensive synthesis flow for the emerging field of logic-in-memory computing Describes automated compilation of programmable logic-in-memory computer architectures Includes several effective optimization algorithm also applicable to classical logic synthesis Investigates unbalanced write traffic in logic-in-memory architectures and describes wear leveling approaches to alleviate it
Autor*in
Saeideh Shirinzadeh
Themen in »In-Memory Computing«
Memristors Memristive Devices and Systems Non-volatile in-memory computing Programmable Logic-in-Memory Spintronics
Stimmen zu »In-Memory Computing«
“This short but very interesting book gives readers plenty of food for thought. ... This book reveals some new possibilities and uncovered areas. We will see the future of in-memory computing development, but the book is also a worthwhile read on what can be done to perform faster computations.” (Dominik Strzalka, Computing Reviews, October 28, 2019)
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