Simulated Annealing for VLSI Design

Beschreibung

This monograph represents a summary of our work in the last two years in applying the method of simulated annealing to the solution of problems that arise in the physical design of VLSI circuits. Our study is experimental in nature, in that we are con cerned with issues such as solution representations, neighborhood structures, cost functions, approximation schemes, and so on, in order to obtain good design results in a reasonable amount of com putation time. We hope that our experiences with the techniques we employed, some of which indeed bear certain similarities for different problems, could be useful as hints and guides for other researchers in applying the method to the solution of other prob lems. Work reported in this monograph was partially supported by the National Science Foundation under grant MIP 87-03273, by the Semiconductor Research Corporation under contract 87-DP- 109, by a grant from the General Electric Company, and by a grant from the Sandia Laboratories.

Autor*in

D.F. Wong

Themen in »Simulated Annealing for VLSI Design«

VLSI algorithms design layout optimization

Stimmen zu »Simulated Annealing for VLSI Design«

`Individuals interested in design automation and, in particular, VLSI design will find this monograph a useful source of information on the application of the simulated annealing method.'
Zentralblatt für Mathematik, 699 (1991)
()

Details

Link teilen