High-Linearity CMOS RF Front-End Circuits

Beschreibung

The rapidly growing wireless communication industry is increasingly
demanding CMOS RF ICs due to their lower costs and higher integration
levels. The RF front-end of such wireless systems often needs to
handle widely disparate signal levels: small desired signals and
large interferers. Therefore, it becomes necessary to have highly
linear circuits to increase the system dynamic range. However,
traditional CMOS circuit designs are usually limited in either their
speed or in their linear performance. New techniques are needed to
meet the demand for high linearity at radio frequencies.

High-Linearity CMOS RF Front-End Circuits presents some unique
techniques to enhance the linearity of both the receiver and
transmitter. For example, using harmonic cancellation techniques, the
linearity of the receiver front-end can be increased by few tens of
dB with only minimal impact on the other circuit parameters. The new
parallel class A&B power amplifier can not only increase the
transmitter's output power in the linear range, but can also result
in significant savings in power consumption.

High-Linearity CMOS RF Front-End Circuits can be used as a textbook
for graduate courses in RF CMOS design and will also be useful as a reference for the
practicing engineer.

This monograph presents techniques to improve the performance of linear integrated circuits (IC) in CMOS at high frequencies. Those circuits are primarily used in radio-frequency (RF) front-ends of wireless communication systems, such as low noise amplifiers (LNA) and mixers in a receiver and power amplifiers (PA) in a transmitter. A novel linearization technique is presented. With a small trade-off of gain and power consumption this technique can improve the linearity of the majority of circuits by tens of dB. Particularly, for modern CMOS processes, most of which has device matching better than 1%, the distortion can be compressed by up to 40 dB at the output. A prototype LNA has been fabricated in a 0.25um CMOS process, with a measured +18 dBm IIP3. This technique improves the dynamic range of a receiver RF front-end by 12 dB. A new class of power amplifier (parallel class A&B) is also presented to extend the linear operation range and save the DC power consumption. It has been shown by both simulations and measurements that the new PA doubles the maximum output power and reduces the DC power consumption by up to 50%.

Autor*in

Yongwang Ding

Themen in »High-Linearity CMOS RF Front-End Circuits«

CMOS circuit design integrated circuit simulation

Stimmen zu »High-Linearity CMOS RF Front-End Circuits«

Details

Link teilen