High-Speed Clock Network Design

Beschreibung

High-Speed Clock Network Design is a collection of design concepts, techniques and research works from the author for clock distribution in microprocessors and high-performance chips. It is organized in 11 chapters.

Autor*in

Qing K. Zhu

Themen in »High-Speed Clock Network Design«

ASIC Flip-Flop Phase Signal VLSI algorithms computer-aided design (CAD) consumption digital design integrated circuit layers microprocessor network networks simulation

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