Fast, Efficient and Predictable Memory Accesses
Optimization Algorithms for Memory Architecture Aware Compilation
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Beschreibung
Fast, Efficient and Predictable Memory Accesses presents techniques for designing fast, energy-efficient and timing predictable memory systems. By using a careful combination of compiler optimizations and architectural improvements, we can achieve more than what would be feasible at one of the levels in isolation. The described optimization algorithms achieve the goals of high performance and low energy consumption. In addition to these benefits, the use of scratchpad memories significantly improves the timing predictability of the entire system, leading to tighter worst case execution time bounds (WCET). The WCET is a relevant design parameter for all timing critical systems. In addition, the book covers algorithms to exploit the power down modes of main memories in SDRAM technology, as well as the execute-in-place feature of Flash memories. The final chapter considers the impact of the register file, which is also part of the memory hierarchy.
Focus on the increasing importance of memory system design in embedded systems Solutions to the problems of energy-inefficient and slow memory systems with unpredictable access times Demonstration of the benefits of exploiting architectural features at the compiler level Unified overview and representation of memory and processor timing, energy and simulation models The first book to consider the positive effects of scratchpad memories on worst case execution time analysis
Autor*in
Lars Wehmeyer
Themen in »Fast, Efficient and Predictable Memory Accesses«
Compiler DRAM Energy Memory RAM Timing Predictability embedded systems processor