Introduction to Advanced System-on-Chip Test Design and Optimization
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Beschreibung
SOC test design and its optimization is the topic of this book, and the aim is to give an introduction to testing, describe the problems related to SOC testing, discuses the modeling granularity and the implementation into EDA (electronic design automation) tools. It first introduces readers to test problems including faults, fault types, design-flow, design-for-test techniques such as scan-testing and Boundary Scan. Then it discusses SOC related problems such as system modeling, test conflicts, power consumption, test access mechanism design, test scheduling and defect-oriented scheduling. The final part focuses on SOC applications, such as integrated test scheduling and TAM design, defect-oriented scheduling, and integrating test design with core selection process. Intended for graduate students and PhD-students working in the test field, the manual also aids researchers and professors who would like to get into the area of SOC testing.
System perspective to SOC test design. Overview of test problems and their modeling Test scheduling overview, extensive reference list Applicable for Master students and PhD-students working in the test field. Could also be good for researchers and professors who would like to get into the area of SOC testing, also for persons in the field who want some references Includes supplementary material: sn.pub/extras
Autor*in
Erik Larsson
Themen in »Introduction to Advanced System-on-Chip Test Design and Optimization«
Boundary Scan SOC test design System-on-Chip Transistor automation consumption integrated circuit