System-on-a-Chip Verification

Beschreibung

System-On-a-Chip Verification: Methodology and Techniques is the first book to cover verification strategies and methodologies for SOC verification from system level verification to the design sign- off. The topics covered include Introduction to the SOC design and verification aspects, System level verification in brief, Block level verification, Analog/mixed signal simulation, Simulation, HW/SW Co-verification, Static netlist verification, Physical verification, and Design sign-off in brief. All the verification aspects are illustrated with a single reference design for Bluetooth application.
System-On-a-Chip Verification: Methodology and Techniques takes a systematic approach that covers the following aspects of verification strategy in each chapter:

1. Explanation of the objective involved in performing verification after a given design step;
2. Features of options available;
3. When to use a particular option;
4. How to select an option; and
5. Limitations of the option.

Autor*in

Prakash Rashinkar

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Bluetooth FPGA Field Programmable Gate Array Hardware Signal Software analog calculus design integrated circuit model model checking simulation system on chip (SoC) verification

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