Digital Phase Lock Loops
Architectures and Applications
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Beschreibung
Digital phase lock loops are critical components of many communication, signal processing and control systems. This exciting new book covers various types of digital phase lock loops. It presents a comprehensive coverage of a new class of digital phase lock loops called the time delay tanlock loop (TDTL). It also details a number of architectures that improve the performance of the TDTL through adaptive techniques that overcome the conflicting requirements of the locking rage and speed of acquisition. These requirements are of paramount importance in many applications including wireless communications, consumer electronics and others. Digital Phase Lock Loops then illustrates the process of converting the TDTL class of digital phase lock loops for implementation on an FPGA-based reconfigurable system. These devices are being utilized in software-defined radio, DSP-based designs and many other communication and electronic systems to implement complex high-speed algorithms. Their flexibility and reconfigurability facilitate rapid prototyping, on-the-fly upgradeability, and code reuse with minimum effort and complexity. The practical real-time results, of the various TDTL architectures, obtained from the reconfigurable implementations are compared with those obtained through simulations with MATLAB/Simulink. The material in this book will be valuable to researchers, graduate students, and practicing engineers.
A wide coverage of digital phase lock loops including a new class called TDTL Theoretical and practical aspects of digital phase lock loops FPGA-based reconfigurable implementation of digital phase lock loop architectures Selected applications of digital phase lock loops Includes supplementary material: sn.pub/extras
Autor*in
Saleh R. Al-Araji
Themen in »Digital Phase Lock Loops«
Digital phase lock loops Digital phase lock loops applications Digital phase lock loops noise analysis FPGA FPGA-based Reconfigurable Systems Filter Frequency estimation Hilbert Transforms Switch Time Delay Digital Tanlock Loops communication complexity development digital signal processor system analysis