Constraint-Based Verification
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Beschreibung
Constraint-Based Verifcation covers the emerging field in functional verification of electronic designs thats is now commonly referred to by this name.
Topics are developed in the context of a wide range of dynamic and static verification approaches including stimulation, emulation and formal methods. The goal is to show how constraints, or assertions, can be used toward automating the generation of testbenches, resulting in a seamless verifcation flow. Topics such as verification coverage, and connection with assertion-based verification are also covered.
Constraint-Based Verification is written for verification engineers, as well as researchers - it explains both methodological and technical issues. Particular stress is given to the latest advances in functional verification.
As the complexity and miniaturization of electronic hardware advances, more time and money is actually now spent on testing and verification than in the preliminary design stage. This practical-oriented guidebook covers both the fundamentals and the techniques of constraint-based testbench automation. The book compares and contrasts constraint-based verification with traditional testbench approaches: test generation (a key concept), simulation monitoring, and coverage. Related aspects of verification languages such as e/vera/PSL/OVL/SVA are also covered. On the technical side, state-of-the art algorithms of test generation, performance optimization, and randomization are explained.
Covers the methodology and state-of-the-art techniques of constrained verification, which is new and popular It relates constrained verification with the also-hot technology called assertion-based design Discussed and clarifies language issues, critical to both the above, which will help the implementation of these languages Includes supplementary material: sn.pub/extras
Autor*in
Jun Yuan
Themen in »Constraint-Based Verification«
Verilog diagnosis formal method formal methods optimization simulation