Fully-Depleted SOI CMOS Circuits and Technology for Ultralow-Power Applications
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Beschreibung
The most important issue confronting CMOS technology is the power explosion of chips arising from the scaling law. Fully-depleted (FD) SOI technology provides a promising low-power solution to chip implementation. Ultralow-power VLSIs, which have a power consumption of less than 10 mW, will be key components of terminals in the coming ubiquitous-IT society. Fully-depleted SOI CMOS Circuits and Technology for Ultralow-Power Applications addresses the problem of reducing the supply voltage of conventional circuits for ultralow-power operation and explains power-efficient MTCMOS circuit design for FD-SOI devices at a supply voltage of 0.5 V. The topics include the minimum required knowledge of the fabrication of SOI substrates; FD-SOI devices and the latest developments in device and process technologies; and ultralow-voltage circuits, such as digital circuits, analog/RF circuits, and DC-DC converters. Each ultra-low-power technique related to devices and circuits is fully explained using figures to help understanding.
Systematically covers ultralow-power circuit-design methods for FD-SOI devices Ultralow-voltage circuits including analog/RF circuits, and DC-DC converters are described in addition to digital circuits Three examples of ultralow-power wireless systems are demonstrated to verify the effectiveness of FD-SOI technology
Autor*in
Takayasu Sakurai
Themen in »Fully-Depleted SOI CMOS Circuits and Technology for Ultralow-Power Applications«
Bluetooth MTCMOS VLSI battery-less application consumption fully-depleted SOI green-energy use integrated circuit metal oxide semiconductur field-effect transistor microprocessor mixed digital-analog circuit reduction of environmental burden self-powered short-range wireless system ubiquitous service