The Verilog® Hardware Description Language

Beschreibung

xv From the Old to the New xvii Acknowledgments xxi 1 Verilog – A Tutorial Introduction 1 Getting Started 2 A Structural Description 2 Simulating the binaryToESeg Driver 4 Creating Ports For the Module 7 Creating a Testbench For a Module 8 11 Behavioral Modeling of Combinational Circuits Procedural Models 12 Rules for Synthesizing Combinational Circuits 13 14 Procedural Modeling of Clocked Sequential Circuits Modeling Finite State Machines 15 Rules for Synthesizing Sequential Systems 18 Non-Blocking Assignment ("

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Donald E. Thomas

Themen in »The Verilog® Hardware Description Language«

Advanced VLSI Describing digital systems Formal verification Hardware Logic design and simulation Simulating digital systems Synthesizing digital systems Thomas and Moorby Verification Verilog logic modeling

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